1. Field of the Disclosure
The disclosed subject matter relates generally to electronic devices having multiple power states and, more particularly, to a method and apparatus for storing an architectural state of a processor in cache memory.
2. Description of the Related Art
Some processors may include multiple central processing unit (CPU) cores and one or more secondary processor cores, such as a graphics processing unit (GPU) cores. To save system power, one or more of these cores can be powered off when not being utilized. For example, a processor core may be powered down when the processing load is light. When the load subsequently increases and the system again requires the use of that processor core, it will power up the processor core and resume executing instructions on that processor core. When a processor core is powered off, the architectural state of that processor core is lost. When the processor core is powered up again, it will require that architectural state be re-established to continue executing instructions. To avoid running lengthy boot code to restore the processor core back to an initialized state, a processor core may save its architectural state before being powered off and then restore that architectural state when being powered up. The processor core stores the architectural state in a location that will retain power across the processor core powered-down period.
This process of saving and restoring architectural state is time-critical for the system. Any time wasted before going into the powered-down state is time that the core could have been already powered down. Reducing the time required for an architectural state save results in increased power savings. Also, any time wasted while restoring the architectural state on power-up adds to the latency in re-establishing the operational state of the processor core, thereby reducing system performance.
The memory location where the architectural state is saved while the processor core is in a low power state must be secure. If a hardware or software entity could maliciously corrupt this architectural state when the processor core is in a low power state, the processor core would restore a corrupted state and could be exposed to a security risk. Conventional processors save the architectural state to various locations to facilitate a lower power state. For example, the processor may save the architectural state to a dedicated static random access memory (“SRAM”) array or to the system memory ((e.g., dynamic random access memory (“DRAM”)). The use of dedicated SRAM allows faster save and restore times and improved security, but requires additional hardware, resulting in increased cost. Saving the architectural state to system memory uses existing memory infrastructure, but increases save and restore times and decreases security as compared to the use of dedicated SRAM.
The use of the same reference symbols in different drawings indicates similar or identical items.